The present invention relates to a method and/or architecture for current sources generally and, more particularly, to a method and/or architecture matching PMOS and NMOS current sources in charge pumps used in PLLs.
Several conventional methods have been implemented to provide current matching between pullup and pulldown sections in charge pump phase lock loop (PLL) circuits. However, most conventional methods have improper matching and a higher output compliance requirement for good matching.
Referring to FIGS. 1(a-c), conventional methods for current generation are shown. FIG. 1a illustrates a circuit 10, FIG. 1b illustrates a circuit 20 and FIG. 1c illustrates a circuit 30. Current matching simulation plots of the circuits 10, 20 and 30 are shown in FIGS. 2(a-c), respectively.
The circuits 10 and 20 are cascode structures that do not provide accurate matching between NMOS and PMOS stacks. In particular, the resistance of the NMOS and PMOS devices that are closest to the supply voltage do not track each other due to differences between NMOS and PMOS devices when they enter saturation. Increasing current through the cascode stage or providing very large size discrimination may obtain better matching. However, the circuits 10 and 20 provide a current source with very low output compliance, particularly if only the NMOS or PMOS source is of interest.
A cascoded output stage provides a large output impedance, which is a general prerequisite for any current reference. One method of generating the cascode voltages PCAS and NCAS and the bias voltages PBIAS and NBIAS is by size discrimination or current discrimination in the two stages. The size discrimination generates unequal bias voltages PBIAS and NBIAS that drive a cascode output stage.
Ideally a constant current (or a multiple) flows through the two stages that generate the bias voltages PBIAS and NBIAS and the cascode voltage PCASC and NCASC. However, a mismatch occurs between the NMOS and PMOS stacks that mirror the cascode and bias voltages. The mismatch can be traced to the devices closest to the supply voltage. The mismatch occurs since the NMOS and PMOS devices can enter saturation at different drain to source voltages (i.e., Vdsnmos does not equal Vdspmos). Therefore, a different output resistance curve is traced by the two references, as shown in FIGS. 2a and 2b. 
The circuits 10 and 20 provide an output compliance range in the region of around 200 mV from either supply voltage. The devices closest to supply voltage operate on the edge of their linear limit (i.e., just as they enter saturation) before the negative feedback blocks any further increase in the drain to source voltage Vds. However, different resistance values for the NMOS and PMOS devices may result. Prior solutions have increased the size discrimination or current discrimination or both in the cascode and bias generation legs and obtained reasonable matching. However, such solutions are not best suited with respect to die area and current consumption constraints.
The circuit 30 requires a compliance voltage of a threshold voltage Vtn or (Vccxe2x88x92Vtp) at the output before a high impedance output is delivered. The circuit 30 eliminates the mismatch associated with the circuits 10 and 20 by operating the devices closest to the supply voltage with a drain to source voltage Vds that is equal to at least a threshold voltage Vt. As Vds greater than =Vt, the devices are pulled well into the saturation regions to provide matching between NMOS and PMOS output references. However, a disadvantage of the circuit 30 is that the minimum output compliance voltage is equal to one threshold voltage Vt from the supply voltage. Thus, the output compliance voltage is Vtn greater than Vcompliance less than (Vccxe2x88x92Vtp).
Generally, charge pumps should have a high output impedance in order to maintain a constant current across a range of control voltages used in frequency synthesis. Therefore, single MOS devices biased with a constant gate voltage are unsuitable due to channel length modulation which causes large mismatches between NMOS and PMOS currents. Such current mismatches can cause different phase offsets at different synthesized frequencies. A cascode device structure is usually a good choice to maintain constant current over a wide range of output voltages.
The present invention concerns an apparatus comprising a pullup circuit, a pulldown circuit, and a control circuit. The pullup circuit may be configured to receive a first and second control signal. The pulldown circuit may be configured to receive a third and fourth control signal. The control circuit may be configured to generate the first, second, third and fourth control signals. The control circuit may comprise (i) a first and second control device coupled between the first and second control signals and a supply and (ii) a third and fourth control device coupled between the third and fourth control signals and the supply.
The objects, features and advantages of the present invention include providing a method and/or architecture for improved current matching in charge pumps that may be used in PLLs that may (i) improve current matching in NMOS and PMOS output stages, (ii) improve a specification margin for static phase offset in single ended charge pump implementations, (iii) have a lower output compliance compared to an otherwise equivalent-performing scheme, (iv) have matching between P and N stacks, (vi) provide less than 1% mismatch within the operating range, (vi) allow tracking between reference and mirror devices and/or (vii) allow compliance limits on an output voltage that are less than Vtn or (Vccxe2x88x92Vtp).